FPGA Based Implementation of Pipelined 32-bit RISC Processor with Floating Point Unit
نویسندگان
چکیده
This paper presents 32-bit RISC processor with floating point unit to be designed using pipelined architecture; through this we can improve the speed of the operation as well as overall performance. This processor is developed especially for Arithmetic operations of both fixed and floating point numbers, branch and logical functions. The proposed architecture is able to prevent pipelining from flushing when branch instruction occurs and able to provide halt support. Floating point operations are widely used these days for many applications ranging from graphics application to medical imaging. Thus, the processor can be used for diversified application area. The necessary code is written in the hardware description language Verilog HDL. Quartus II 10.1 suite is used for software development; Modelsim is used for simulations and then implementation on Altera DE 2 FPGA board.
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